1. Field of the Invention
This invention relates to a method of inserting a data load into an instruction sequence on a computer system, and particularly to such a method which is also suitable for use in processing elements which comprise systems based on reduced instruction set computer (RISC) architecture.
2. Description of the Related Art
Data synchronization methods suitable for non-RISC computer systems, as known in the prior art, include methods which allow synchronizing of data to be done in memory; namely, those in which each memory element is provided with a flag which indicates the status of that data so that data access requests are held until certain conditions of the flags are met. The benefits of such methods include that the synchronizing of data among processes is fast since processing is based on individual pieces of data and can be accomplished with simple code.
However, such methods of synchronizing of data on memory are difficult to apply to processing elements, such as those in the above RISC systems, which employ architecture based on register operations which have recently attracted much attention. To begin with, in such register operation-based architecture, since the registers are tightly bound to the processing elements, there are problems with arbitration with respect to the execution unit as well as difficulties with the access path, so external access to registers is hard to implement. Furthermore, registers are an expensive resource and their capacity is limited for achieving a wide data transmission band-width and fast access so when a register has to wait for data for long periods, use of a memory element for the register is unavoidable, but an answer to the problem of just how the synchronizing of data at this time is to be accomplished has yet to be reported.